1. Field of the Invention
The present invention relates to technology for programming a nonvolatile semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are devices in which data can be stored and from which stored data can be retrieved. Semiconductor memory devices can be classified into volatile memory and nonvolatile memory. The volatile memory needs a power supply to retain data while the nonvolatile memory can retain data even when power is removed. Therefore, the nonvolatile memory devices have been widely used in applications in which power can be interrupted suddenly.
The nonvolatile memory devices comprise electrically erasable and programmable ROM cells, known as flash EEPROM cells. FIG. 1 shows a vertical cross-section of the flash EEPROM cell 10. Referring to FIG. 1, a deep n-type well 12 is formed in a bulk region or a P-type substrate 11, and a p-type well 13 is formed in the n-type well 12. An N-type source region 14 and an N-type drain region 15 are formed in the P-type well 13. A p-type channel region is formed between the source region 14 and the drain region 15. A floating gate 17, which is insulated by an insulating layer 16, is formed on the P-type channel region. A control gate 19, which is insulated by another insulating layer 18, is formed above the floating gate 17.
FIG. 2 shows threshold voltages of the flash EEPROM cell 10 during program and erase operations. Referring to FIG. 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7V) during the program operation, and has a lower threshold voltage range (about 1 to 3V) during the erase operation.
Referring to FIGS. 1 and 2, during the program operation, hot electrons need to be injected from the channel region adjacent to the drain region 15 to the floating gate electrode, so that the threshold voltage of the EEPROM cell increases. In contrast, during the erase operation, the hot electrons injected into the floating gate 17 during the program operation need to be removed, so that the threshold voltage of the EEPROM cell decreases. Therefore, the threshold voltages of the EEPROM cell are varied after the program and erase operation.
FIG. 3 shows a typical flash memory array architecture using a NOR structure. Referring to FIG. 3, the flash memory array 30 includes a plurality of flash memory cells 31 to 33 that are defined in regions where a plurality of word lines WL1 to WL4, a plurality of bit lines BL1 to BL4, and a source line SL1 cross. Two adjacent flash memory cells 31 and 32 in is FIG. 3, which are respectively coupled to the same word line WL1 and different bit lines BL1 and BL2, share the same source SL1. The NOR flash memory device in general is configured such that 8 or 16 different bit lines can share one common source line.
During a program operation, a program voltage VPP (e.g., 4V) is applied to a bit line connected to a selected cell transistor, a ground voltage VSS is applied to a source line connected to the selected cell transistor, and a high voltage VH (e.g., 9V) is applied to a word line connected to the selected cell transistor. Meanwhile, the ground voltage VSS is applied to a word line connected to an unselected cell transistor. For example, if the memory cell 31 is selected to be programmed and the memory cell 32 is selected not to be programmed, the program voltage VPP is applied to the bit line BL1, the ground voltage VSS is applied to the source line SL1, the bit line BL2 and other word lines WL2 to WL4, while the high voltage VH is applied to the word line WL1. Under this condition, the cell transistor 31 is programmed to high threshold voltage. However, because the program voltage VPP is applied to all cells connected to the same bit line BL1, the state of another unselected memory cell 33 adjacent to the cell 31 might unintentionally be affected. This condition is usually called “program disturb.” The threshold voltage distribution of the unselected memory cells is shifted to the right when the program disturb occurs.
Thus, there is a need for a new mechanism to reduce the impact of program disturb.